A ${0.35}~\mu{\rm m}$ Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links

C. Zamarreno-Ramos, T. Serrano-Gotarredona, B. Linares-Barranco

doi:10.1109/tbcas.2012.2186136

CrossrefKarta ta’ informazzjoni

A ${0.35}~\mu{\rm m}$ Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links

C. Zamarreno-Ramos, T. Serrano-Gotarredona, B. Linares-Barranco

IEEE Transactions on Biomedical Circuits and Systems · 2012-10 · 6 (5) · 486-497

DOI: 10.1109/tbcas.2012.2186136 ↗

Astratt Dettalji biblijografiċi

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Dettalji biblijografiċi

Awturi/Awturiċi: C. Zamarreno-Ramos, T. Serrano-Gotarredona, B. Linares-Barranco
Ġurnal: IEEE Transactions on Biomedical Circuits and Systems
Sena tal-pubblikazzjoni: 2012
Volum / Ħarġa: 6 / 5
Paġni: 486-497
Pubblikatur: Institute of Electrical and Electronics Engineers (IEEE)
DOI: 10.1109/tbcas.2012.2186136
ISSN: 1932-4545; 1940-9990
Sors: Crossref

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